Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: LIN64 Target Device: xc6slx9
Project ID (random number) bd54f6f25c1b40a896430d6a1ea7d0bd.CB4CA30C6BB66831111BF97BC0465892.4 Target Package: tqg144
Registration ID 211038720_0_0_758 Target Speed: -2
Date Generated 2021-05-26T11:42:54 Tool Flow ISE
 
User Environment
OS Name openSUSE OS Release openSUSE Leap 15.0
CPU Name Intel(R) Core(TM) i5-2540M CPU @ 2.60GHz CPU Speed 2593.960 MHz
OS Name openSUSE OS Release openSUSE Leap 15.0
CPU Name Intel(R) Core(TM) i5-2540M CPU @ 2.60GHz CPU Speed 2593.960 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=9
  • 16-bit adder=8
  • 16-bit subtractor=1
 Counters=2
  • 12-bit up counter=1
  • 25-bit up counter=1
 FSMs=2 Multiplexers=30
  • 1-bit 2-to-1 multiplexer=6
  • 16-bit 2-to-1 multiplexer=24
 Registers=226
  • Flip-Flops=226
 		MiscellaneousStatistics
  • AGG_BONDED_IO=69
  • AGG_IO=69
  • AGG_LOCED_IO=69
  • AGG_SLICE=1386
  • NUM_BONDED_IOB=69
  • NUM_BSFULL=3665
  • NUM_BSLUTONLY=393
  • NUM_BSREGONLY=696
  • NUM_BSUSED=4754
  • NUM_BUFG=2
  • NUM_DPRAM_O5ANDO6=256
  • NUM_DSP48A1=16
  • NUM_LOCED_IOB=69
  • NUM_LOGIC_O5ANDO6=1524
  • NUM_LOGIC_O5ONLY=180
  • NUM_LOGIC_O6ONLY=1176
  • NUM_LUT_RT_DRIVES_CARRY4=12
  • NUM_LUT_RT_DRIVES_FLOP=459
  • NUM_LUT_RT_EXO5=455
  • NUM_LUT_RT_EXO6=12
  • NUM_LUT_RT_O5=194
  • NUM_LUT_RT_O5ANDO6=4
  • NUM_LUT_RT_O6=173
  • NUM_RAMB16BWER=17
  • NUM_RAMB8BWER=8
  • NUM_SLICEL=396
  • NUM_SLICEM=179
  • NUM_SLICEX=811
  • NUM_SLICE_CARRY4=383
  • NUM_SLICE_CONTROLSET=208
  • NUM_SLICE_CYINIT=6694
  • NUM_SLICE_F7MUX=13
  • NUM_SLICE_FF=6003
  • NUM_SLICE_LATCH=24
  • NUM_SLICE_UNUSEDCTRL=17
  • NUM_SRL_O5ANDO6=424
  • NUM_SRL_O6ONLY=27
  • NUM_UNUSABLE_FF_BELS=594
  • Xilinx Core cic_compiler_v3_0, Xilinx CORE Generator 14.7=8
  • Xilinx Core dds_compiler_v4_0, Xilinx CORE Generator 14.7=1
  • Xilinx Core fifo_generator_v9_3, Xilinx CORE Generator 14.7=9
  • Xilinx Core fir_compiler_v6_3, Xilinx CORE Generator 14.7=8
  • Xilinx Core mult_gen_v11_2, Xilinx CORE Generator 14.7=8
 		NetStatistics
  • NumNets_Active=7451
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=225
  • NumNodesOfType_Active_BOUNCEIN=934
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=14
  • NumNodesOfType_Active_CLKPIN=1385
  • NumNodesOfType_Active_CLKPINFEED=14
  • NumNodesOfType_Active_CNTRLPIN=633
  • NumNodesOfType_Active_DOUBLE=11617
  • NumNodesOfType_Active_GENERIC=143
  • NumNodesOfType_Active_GLOBAL=173
  • NumNodesOfType_Active_INPUT=2685
  • NumNodesOfType_Active_IOBIN2OUT=83
  • NumNodesOfType_Active_IOBOUTPUT=83
  • NumNodesOfType_Active_LUTINPUT=12843
  • NumNodesOfType_Active_OUTBOUND=7557
  • NumNodesOfType_Active_OUTPUT=7350
  • NumNodesOfType_Active_PADINPUT=24
  • NumNodesOfType_Active_PADOUTPUT=60
  • NumNodesOfType_Active_PINBOUNCE=5400
  • NumNodesOfType_Active_PINFEED=15852
  • NumNodesOfType_Active_QUAD=8892
  • NumNodesOfType_Active_REGINPUT=2315
  • NumNodesOfType_Active_SINGLE=13273
  • NumNodesOfType_Gnd_BOUNCEACROSS=80
  • NumNodesOfType_Gnd_BOUNCEIN=543
  • NumNodesOfType_Gnd_DOUBLE=154
  • NumNodesOfType_Gnd_HGNDOUT=263
  • NumNodesOfType_Gnd_INPUT=2780
  • NumNodesOfType_Gnd_LUTINPUT=915
  • NumNodesOfType_Gnd_OUTBOUND=68
  • NumNodesOfType_Gnd_OUTPUT=79
  • NumNodesOfType_Gnd_PINBOUNCE=980
  • NumNodesOfType_Gnd_PINFEED=3396
  • NumNodesOfType_Gnd_QUAD=11
  • NumNodesOfType_Gnd_REGINPUT=45
  • NumNodesOfType_Gnd_SINGLE=213
  • NumNodesOfType_Vcc_CNTRLPIN=43
  • NumNodesOfType_Vcc_GENERIC=1
  • NumNodesOfType_Vcc_HVCCOUT=654
  • NumNodesOfType_Vcc_INPUT=116
  • NumNodesOfType_Vcc_IOBIN2OUT=1
  • NumNodesOfType_Vcc_IOBOUTPUT=1
  • NumNodesOfType_Vcc_KVCCOUT=149
  • NumNodesOfType_Vcc_LUTINPUT=3302
  • NumNodesOfType_Vcc_PADINPUT=1
  • NumNodesOfType_Vcc_PINBOUNCE=77
  • NumNodesOfType_Vcc_PINFEED=3395
  • NumNodesOfType_Vcc_REGINPUT=10
 SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=32
  • IOB-IOBS=37
  • SLICEL-SLICEM=131
  • SLICEX-SLICEL=84
  • SLICEX-SLICEM=48
 		SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • CARRY4=383
  • DSP48A1=16
  • DSP48A1_DSP48A1=16
  • FF_SR=1679
  • HARD0=16
  • HARD1=45
  • IOB=69
  • IOB_IMUX=60
  • IOB_INBUF=60
  • IOB_OUTBUF=17
  • LUT5=2355
  • LUT6=2886
  • LUT_OR_MEM5=682
  • LUT_OR_MEM6=710
  • PAD=69
  • RAMB16BWER=17
  • RAMB16BWER_RAMB16BWER=17
  • RAMB8BWER=8
  • RAMB8BWER_RAMB8BWER=8
  • REG_SR=4348
  • SELMUX2_1=13
  • SLICEL=396
  • SLICEM=179
  • SLICEX=811
 
Configuration Data
DSP48A1
  • CEA=[CEA_INV:0] [CEA:16]
  • CEB=[CEB_INV:0] [CEB:16]
  • CEC=[CEC:16] [CEC_INV:0]
  • CECARRYIN=[CECARRYIN_INV:0] [CECARRYIN:16]
  • CED=[CED_INV:0] [CED:16]
  • CEM=[CEM_INV:0] [CEM:16]
  • CEOPMODE=[CEOPMODE_INV:0] [CEOPMODE:16]
  • CEP=[CEP:16] [CEP_INV:0]
  • CLK=[CLK:16] [CLK_INV:0]
  • RSTA=[RSTA:16] [RSTA_INV:0]
  • RSTB=[RSTB:16] [RSTB_INV:0]
  • RSTC=[RSTC_INV:0] [RSTC:16]
  • RSTCARRYIN=[RSTCARRYIN_INV:0] [RSTCARRYIN:16]
  • RSTD=[RSTD_INV:0] [RSTD:16]
  • RSTM=[RSTM:16] [RSTM_INV:0]
  • RSTOPMODE=[RSTOPMODE_INV:0] [RSTOPMODE:16]
  • RSTP=[RSTP_INV:0] [RSTP:16]
 DSP48A1_DSP48A1
  • A0REG=[0:16]
  • A1REG=[1:16]
  • B0REG=[1:16]
  • B1REG=[0:8] [1:8]
  • B_INPUT=[DIRECT:16]
  • CARRYINREG=[0:16]
  • CARRYINSEL=[OPMODE5:16]
  • CARRYOUTREG=[0:16]
  • CEA=[CEA_INV:0] [CEA:16]
  • CEB=[CEB_INV:0] [CEB:16]
  • CEC=[CEC:16] [CEC_INV:0]
  • CECARRYIN=[CECARRYIN_INV:0] [CECARRYIN:16]
  • CED=[CED_INV:0] [CED:16]
  • CEM=[CEM_INV:0] [CEM:16]
  • CEOPMODE=[CEOPMODE_INV:0] [CEOPMODE:16]
  • CEP=[CEP:16] [CEP_INV:0]
  • CLK=[CLK:16] [CLK_INV:0]
  • CREG=[0:8] [1:8]
  • DREG=[0:8] [1:8]
  • MREG=[1:16]
  • OPMODEREG=[0:8] [1:8]
  • PREG=[1:16]
  • RSTA=[RSTA:16] [RSTA_INV:0]
  • RSTB=[RSTB:16] [RSTB_INV:0]
  • RSTC=[RSTC_INV:0] [RSTC:16]
  • RSTCARRYIN=[RSTCARRYIN_INV:0] [RSTCARRYIN:16]
  • RSTD=[RSTD_INV:0] [RSTD:16]
  • RSTM=[RSTM:16] [RSTM_INV:0]
  • RSTOPMODE=[RSTOPMODE_INV:0] [RSTOPMODE:16]
  • RSTP=[RSTP_INV:0] [RSTP:16]
  • RSTTYPE=[SYNC:16]
 FF_SR
  • CK=[CK:1679] [CK_INV:0]
  • SRINIT=[SRINIT0:1648] [SRINIT1:31]
  • SYNC_ATTR=[ASYNC:816] [SYNC:863]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:17]
  • SLEW=[SLOW:17]
  • SUSPEND=[3STATE:17]
 LUT_OR_MEM5
  • CLK=[CLK:680] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:2] [RAM:680]
  • RAMMODE=[SRL16:424] [DPRAM32:256]
 LUT_OR_MEM6
  • CLK=[CLK:707] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:3] [RAM:707]
  • RAMMODE=[SRL16:451] [DPRAM32:256]
 RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:17]
  • CLKB=[CLKB_INV:0] [CLKB:17]
  • ENA=[ENA_INV:0] [ENA:17]
  • ENB=[ENB_INV:0] [ENB:17]
  • REGCEA=[REGCEA_INV:0] [REGCEA:17]
  • REGCEB=[REGCEB_INV:0] [REGCEB:17]
  • RSTA=[RSTA:17] [RSTA_INV:0]
  • RSTB=[RSTB:17] [RSTB_INV:0]
  • WEA0=[WEA0:17] [WEA0_INV:0]
  • WEA1=[WEA1:17] [WEA1_INV:0]
  • WEA2=[WEA2:17] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:17]
  • WEB0=[WEB0:17] [WEB0_INV:0]
  • WEB1=[WEB1:17] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:17]
  • WEB3=[WEB3:17] [WEB3_INV:0]
 RAMB16BWER_RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:17]
  • CLKB=[CLKB_INV:0] [CLKB:17]
  • DATA_WIDTH_A=[2:16] [18:1]
  • DATA_WIDTH_B=[1:16] [18:1]
  • DOA_REG=[0:16] [1:1]
  • DOB_REG=[0:16] [1:1]
  • ENA=[ENA_INV:0] [ENA:17]
  • ENB=[ENB_INV:0] [ENB:17]
  • EN_RSTRAM_A=[FALSE:16] [TRUE:1]
  • EN_RSTRAM_B=[TRUE:17]
  • RAM_MODE=[TDP:17]
  • REGCEA=[REGCEA_INV:0] [REGCEA:17]
  • REGCEB=[REGCEB_INV:0] [REGCEB:17]
  • RSTA=[RSTA:17] [RSTA_INV:0]
  • RSTB=[RSTB:17] [RSTB_INV:0]
  • RSTTYPE=[SYNC:17]
  • RST_PRIORITY_A=[CE:17]
  • RST_PRIORITY_B=[CE:17]
  • WEA0=[WEA0:17] [WEA0_INV:0]
  • WEA1=[WEA1:17] [WEA1_INV:0]
  • WEA2=[WEA2:17] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:17]
  • WEB0=[WEB0:17] [WEB0_INV:0]
  • WEB1=[WEB1:17] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:17]
  • WEB3=[WEB3:17] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:17]
  • WRITE_MODE_B=[WRITE_FIRST:17]
 RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:8] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:8]
  • ENAWREN=[ENAWREN:8] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:8]
  • REGCEA=[REGCEA_INV:0] [REGCEA:8]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:8]
  • RSTA=[RSTA:8] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:8] [RSTBRST_INV:0]
  • WEAWEL0=[WEAWEL0:8] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:8]
  • WEBWEU0=[WEBWEU0:8] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:8] [WEBWEU1_INV:0]
 RAMB8BWER_RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:8] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:8]
  • DATA_WIDTH_A=[36:8]
  • DATA_WIDTH_B=[36:8]
  • DOA_REG=[0:8]
  • DOB_REG=[0:8]
  • ENAWREN=[ENAWREN:8] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:8]
  • EN_RSTRAM_A=[TRUE:8]
  • EN_RSTRAM_B=[TRUE:8]
  • RAM_MODE=[SDP:8]
  • REGCEA=[REGCEA_INV:0] [REGCEA:8]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:8]
  • RSTA=[RSTA:8] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:8] [RSTBRST_INV:0]
  • RSTTYPE=[SYNC:8]
  • RST_PRIORITY_A=[CE:8]
  • RST_PRIORITY_B=[CE:8]
  • WEAWEL0=[WEAWEL0:8] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:8]
  • WEBWEU0=[WEBWEU0:8] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:8] [WEBWEU1_INV:0]
  • WRITE_MODE_A=[READ_FIRST:8]
  • WRITE_MODE_B=[READ_FIRST:8]
 REG_SR
  • CK=[CK:4324] [CK_INV:24]
  • LATCH_OR_FF=[FF:4324] [LATCH:24]
  • SRINIT=[SRINIT0:4150] [SRINIT1:198]
  • SYNC_ATTR=[ASYNC:2979] [SYNC:1369]
 SLICEL
  • CLK=[CLK:388] [CLK_INV:0]
 SLICEM
  • CLK=[CLK:179] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:796] [CLK_INV:6]
 
Pin Data
BUFG
  • I0=2
  • O=2
 BUFG_BUFG
  • I0=2
  • O=2
 CARRY4
  • CIN=314
  • CO2=2
  • CO3=316
  • CYINIT=69
  • DI0=373
  • DI1=364
  • DI2=339
  • DI3=316
  • O0=329
  • O1=362
  • O2=353
  • O3=328
  • S0=383
  • S1=373
  • S2=364
  • S3=337
 DSP48A1
  • A0=16
  • A1=16
  • A10=16
  • A11=16
  • A12=16
  • A13=16
  • A14=16
  • A15=16
  • A16=16
  • A17=16
  • A2=16
  • A3=16
  • A4=16
  • A5=16
  • A6=16
  • A7=16
  • A8=16
  • A9=16
  • B0=16
  • B1=16
  • B10=16
  • B11=16
  • B12=16
  • B13=16
  • B14=16
  • B15=16
  • B16=16
  • B17=16
  • B2=16
  • B3=16
  • B4=16
  • B5=16
  • B6=16
  • B7=16
  • B8=16
  • B9=16
  • C0=16
  • C1=16
  • C10=16
  • C11=16
  • C12=16
  • C13=16
  • C14=16
  • C15=16
  • C16=16
  • C17=16
  • C18=16
  • C19=16
  • C2=16
  • C20=16
  • C21=16
  • C22=16
  • C23=16
  • C24=16
  • C25=16
  • C26=16
  • C27=16
  • C28=16
  • C29=16
  • C3=16
  • C30=16
  • C31=16
  • C32=16
  • C33=16
  • C34=16
  • C35=16
  • C36=16
  • C37=16
  • C38=16
  • C39=16
  • C4=16
  • C40=16
  • C41=16
  • C42=16
  • C43=16
  • C44=16
  • C45=16
  • C46=16
  • C47=16
  • C5=16
  • C6=16
  • C7=16
  • C8=16
  • C9=16
  • CEA=16
  • CEB=16
  • CEC=16
  • CECARRYIN=16
  • CED=16
  • CEM=16
  • CEOPMODE=16
  • CEP=16
  • CLK=16
  • D0=16
  • D1=16
  • D10=16
  • D11=16
  • D12=16
  • D13=16
  • D14=16
  • D15=16
  • D16=16
  • D17=16
  • D2=16
  • D3=16
  • D4=16
  • D5=16
  • D6=16
  • D7=16
  • D8=16
  • D9=16
  • OPMODE0=16
  • OPMODE1=16
  • OPMODE2=16
  • OPMODE3=16
  • OPMODE4=16
  • OPMODE5=16
  • OPMODE6=16
  • OPMODE7=16
  • P13=8
  • P14=8
  • P15=8
  • P16=8
  • P17=16
  • P18=16
  • P19=16
  • P20=16
  • P21=16
  • P22=16
  • P23=16
  • P24=16
  • P25=16
  • P26=16
  • P27=16
  • P28=16
  • P29=8
  • P30=8
  • P31=8
  • P32=8
  • RSTA=16
  • RSTB=16
  • RSTC=16
  • RSTCARRYIN=16
  • RSTD=16
  • RSTM=16
  • RSTOPMODE=16
  • RSTP=16
 DSP48A1_DSP48A1
  • A0=16
  • A1=16
  • A10=16
  • A11=16
  • A12=16
  • A13=16
  • A14=16
  • A15=16
  • A16=16
  • A17=16
  • A2=16
  • A3=16
  • A4=16
  • A5=16
  • A6=16
  • A7=16
  • A8=16
  • A9=16
  • B0=16
  • B1=16
  • B10=16
  • B11=16
  • B12=16
  • B13=16
  • B14=16
  • B15=16
  • B16=16
  • B17=16
  • B2=16
  • B3=16
  • B4=16
  • B5=16
  • B6=16
  • B7=16
  • B8=16
  • B9=16
  • C0=16
  • C1=16
  • C10=16
  • C11=16
  • C12=16
  • C13=16
  • C14=16
  • C15=16
  • C16=16
  • C17=16
  • C18=16
  • C19=16
  • C2=16
  • C20=16
  • C21=16
  • C22=16
  • C23=16
  • C24=16
  • C25=16
  • C26=16
  • C27=16
  • C28=16
  • C29=16
  • C3=16
  • C30=16
  • C31=16
  • C32=16
  • C33=16
  • C34=16
  • C35=16
  • C36=16
  • C37=16
  • C38=16
  • C39=16
  • C4=16
  • C40=16
  • C41=16
  • C42=16
  • C43=16
  • C44=16
  • C45=16
  • C46=16
  • C47=16
  • C5=16
  • C6=16
  • C7=16
  • C8=16
  • C9=16
  • CEA=16
  • CEB=16
  • CEC=16
  • CECARRYIN=16
  • CED=16
  • CEM=16
  • CEOPMODE=16
  • CEP=16
  • CLK=16
  • D0=16
  • D1=16
  • D10=16
  • D11=16
  • D12=16
  • D13=16
  • D14=16
  • D15=16
  • D16=16
  • D17=16
  • D2=16
  • D3=16
  • D4=16
  • D5=16
  • D6=16
  • D7=16
  • D8=16
  • D9=16
  • OPMODE0=16
  • OPMODE1=16
  • OPMODE2=16
  • OPMODE3=16
  • OPMODE4=16
  • OPMODE5=16
  • OPMODE6=16
  • OPMODE7=16
  • P13=8
  • P14=8
  • P15=8
  • P16=8
  • P17=16
  • P18=16
  • P19=16
  • P20=16
  • P21=16
  • P22=16
  • P23=16
  • P24=16
  • P25=16
  • P26=16
  • P27=16
  • P28=16
  • P29=8
  • P30=8
  • P31=8
  • P32=8
  • RSTA=16
  • RSTB=16
  • RSTC=16
  • RSTCARRYIN=16
  • RSTD=16
  • RSTM=16
  • RSTOPMODE=16
  • RSTP=16
 FF_SR
  • CE=477
  • CK=1679
  • D=1679
  • Q=1679
  • SR=130
 HARD0
  • 0=16
 HARD1
  • 1=45
 IOB
  • I=60
  • O=17
  • PAD=69
  • T=8
 IOB_IMUX
  • I=60
  • OUT=60
 IOB_INBUF
  • OUT=60
  • PAD=60
 IOB_OUTBUF
  • IN=17
  • OUT=17
  • TRI=8
 LUT5
  • A1=381
  • A2=428
  • A3=1443
  • A4=277
  • A5=1628
  • O5=2355
 LUT6
  • A1=545
  • A2=863
  • A3=2162
  • A4=2577
  • A5=2610
  • A6=2804
  • O6=2886
 LUT_OR_MEM5
  • A1=680
  • A2=682
  • A3=682
  • A4=682
  • A5=682
  • CLK=680
  • DI1=680
  • O5=554
  • WA1=256
  • WA2=256
  • WA3=256
  • WA4=256
  • WA5=256
  • WE=680
 LUT_OR_MEM6
  • A1=707
  • A2=708
  • A3=709
  • A4=710
  • A5=710
  • A6=710
  • CLK=707
  • DI2=707
  • O6=582
  • WA1=256
  • WA2=256
  • WA3=256
  • WA4=256
  • WA5=256
  • WA6=256
  • WE=707
 PAD
  • PAD=69
 RAMB16BWER
  • ADDRA0=16
  • ADDRA1=16
  • ADDRA10=17
  • ADDRA11=17
  • ADDRA12=17
  • ADDRA13=17
  • ADDRA2=16
  • ADDRA3=16
  • ADDRA4=17
  • ADDRA5=17
  • ADDRA6=17
  • ADDRA7=17
  • ADDRA8=17
  • ADDRA9=17
  • ADDRB0=16
  • ADDRB1=16
  • ADDRB10=17
  • ADDRB11=17
  • ADDRB12=17
  • ADDRB13=17
  • ADDRB2=16
  • ADDRB3=16
  • ADDRB4=17
  • ADDRB5=17
  • ADDRB6=17
  • ADDRB7=17
  • ADDRB8=17
  • ADDRB9=17
  • CLKA=17
  • CLKB=17
  • DIA0=17
  • DIA1=17
  • DIA10=17
  • DIA11=17
  • DIA12=17
  • DIA13=17
  • DIA14=17
  • DIA15=17
  • DIA16=16
  • DIA17=16
  • DIA18=16
  • DIA19=16
  • DIA2=17
  • DIA20=16
  • DIA21=16
  • DIA22=16
  • DIA23=16
  • DIA24=16
  • DIA25=16
  • DIA26=16
  • DIA27=16
  • DIA28=16
  • DIA29=16
  • DIA3=17
  • DIA30=16
  • DIA31=16
  • DIA4=17
  • DIA5=17
  • DIA6=17
  • DIA7=17
  • DIA8=17
  • DIA9=17
  • DIB0=16
  • DIB1=16
  • DIB10=16
  • DIB11=16
  • DIB12=16
  • DIB13=16
  • DIB14=16
  • DIB15=16
  • DIB16=16
  • DIB17=16
  • DIB18=16
  • DIB19=16
  • DIB2=16
  • DIB20=16
  • DIB21=16
  • DIB22=16
  • DIB23=16
  • DIB24=16
  • DIB25=16
  • DIB26=16
  • DIB27=16
  • DIB28=16
  • DIB29=16
  • DIB3=16
  • DIB30=16
  • DIB31=16
  • DIB4=16
  • DIB5=16
  • DIB6=16
  • DIB7=16
  • DIB8=16
  • DIB9=16
  • DIPA0=17
  • DIPA1=17
  • DIPA2=16
  • DIPA3=16
  • DIPB0=16
  • DIPB1=16
  • DIPB2=16
  • DIPB3=16
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOB0=17
  • DOB1=1
  • DOB10=1
  • DOB11=1
  • DOB12=1
  • DOB2=1
  • DOB3=1
  • DOB4=1
  • DOB5=1
  • DOB6=1
  • DOB7=1
  • DOB8=1
  • DOB9=1
  • ENA=17
  • ENB=17
  • REGCEA=17
  • REGCEB=17
  • RSTA=17
  • RSTB=17
  • WEA0=17
  • WEA1=17
  • WEA2=17
  • WEA3=17
  • WEB0=17
  • WEB1=17
  • WEB2=17
  • WEB3=17
 RAMB16BWER_RAMB16BWER
  • ADDRA0=16
  • ADDRA1=16
  • ADDRA10=17
  • ADDRA11=17
  • ADDRA12=17
  • ADDRA13=17
  • ADDRA2=16
  • ADDRA3=16
  • ADDRA4=17
  • ADDRA5=17
  • ADDRA6=17
  • ADDRA7=17
  • ADDRA8=17
  • ADDRA9=17
  • ADDRB0=16
  • ADDRB1=16
  • ADDRB10=17
  • ADDRB11=17
  • ADDRB12=17
  • ADDRB13=17
  • ADDRB2=16
  • ADDRB3=16
  • ADDRB4=17
  • ADDRB5=17
  • ADDRB6=17
  • ADDRB7=17
  • ADDRB8=17
  • ADDRB9=17
  • CLKA=17
  • CLKB=17
  • DIA0=17
  • DIA1=17
  • DIA10=17
  • DIA11=17
  • DIA12=17
  • DIA13=17
  • DIA14=17
  • DIA15=17
  • DIA16=16
  • DIA17=16
  • DIA18=16
  • DIA19=16
  • DIA2=17
  • DIA20=16
  • DIA21=16
  • DIA22=16
  • DIA23=16
  • DIA24=16
  • DIA25=16
  • DIA26=16
  • DIA27=16
  • DIA28=16
  • DIA29=16
  • DIA3=17
  • DIA30=16
  • DIA31=16
  • DIA4=17
  • DIA5=17
  • DIA6=17
  • DIA7=17
  • DIA8=17
  • DIA9=17
  • DIB0=16
  • DIB1=16
  • DIB10=16
  • DIB11=16
  • DIB12=16
  • DIB13=16
  • DIB14=16
  • DIB15=16
  • DIB16=16
  • DIB17=16
  • DIB18=16
  • DIB19=16
  • DIB2=16
  • DIB20=16
  • DIB21=16
  • DIB22=16
  • DIB23=16
  • DIB24=16
  • DIB25=16
  • DIB26=16
  • DIB27=16
  • DIB28=16
  • DIB29=16
  • DIB3=16
  • DIB30=16
  • DIB31=16
  • DIB4=16
  • DIB5=16
  • DIB6=16
  • DIB7=16
  • DIB8=16
  • DIB9=16
  • DIPA0=17
  • DIPA1=17
  • DIPA2=16
  • DIPA3=16
  • DIPB0=16
  • DIPB1=16
  • DIPB2=16
  • DIPB3=16
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOB0=17
  • DOB1=1
  • DOB10=1
  • DOB11=1
  • DOB12=1
  • DOB2=1
  • DOB3=1
  • DOB4=1
  • DOB5=1
  • DOB6=1
  • DOB7=1
  • DOB8=1
  • DOB9=1
  • ENA=17
  • ENB=17
  • REGCEA=17
  • REGCEB=17
  • RSTA=17
  • RSTB=17
  • WEA0=17
  • WEA1=17
  • WEA2=17
  • WEA3=17
  • WEB0=17
  • WEB1=17
  • WEB2=17
  • WEB3=17
 RAMB8BWER
  • ADDRAWRADDR0=8
  • ADDRAWRADDR1=8
  • ADDRAWRADDR10=8
  • ADDRAWRADDR11=8
  • ADDRAWRADDR12=8
  • ADDRAWRADDR2=8
  • ADDRAWRADDR3=8
  • ADDRAWRADDR4=8
  • ADDRAWRADDR5=8
  • ADDRAWRADDR6=8
  • ADDRAWRADDR7=8
  • ADDRAWRADDR8=8
  • ADDRAWRADDR9=8
  • ADDRBRDADDR0=8
  • ADDRBRDADDR1=8
  • ADDRBRDADDR10=8
  • ADDRBRDADDR11=8
  • ADDRBRDADDR12=8
  • ADDRBRDADDR2=8
  • ADDRBRDADDR3=8
  • ADDRBRDADDR4=8
  • ADDRBRDADDR5=8
  • ADDRBRDADDR6=8
  • ADDRBRDADDR7=8
  • ADDRBRDADDR8=8
  • ADDRBRDADDR9=8
  • CLKAWRCLK=8
  • CLKBRDCLK=8
  • DIADI0=8
  • DIADI1=8
  • DIADI10=8
  • DIADI11=8
  • DIADI12=8
  • DIADI13=8
  • DIADI14=8
  • DIADI15=8
  • DIADI2=8
  • DIADI3=8
  • DIADI4=8
  • DIADI5=8
  • DIADI6=8
  • DIADI7=8
  • DIADI8=8
  • DIADI9=8
  • DIBDI0=8
  • DIBDI1=8
  • DIBDI10=8
  • DIBDI11=8
  • DIBDI12=8
  • DIBDI13=8
  • DIBDI14=8
  • DIBDI15=8
  • DIBDI2=8
  • DIBDI3=8
  • DIBDI4=8
  • DIBDI5=8
  • DIBDI6=8
  • DIBDI7=8
  • DIBDI8=8
  • DIBDI9=8
  • DIPADIP0=8
  • DIPADIP1=8
  • DIPBDIP0=8
  • DIPBDIP1=8
  • DOADO0=8
  • DOADO1=8
  • DOADO10=8
  • DOADO11=8
  • DOADO2=8
  • DOADO3=8
  • DOADO8=8
  • DOADO9=8
  • DOBDO0=8
  • DOBDO1=8
  • DOBDO10=8
  • DOBDO11=8
  • DOBDO2=8
  • DOBDO3=8
  • DOBDO8=8
  • DOBDO9=8
  • ENAWREN=8
  • ENBRDEN=8
  • REGCEA=8
  • REGCEBREGCE=8
  • RSTA=8
  • RSTBRST=8
  • WEAWEL0=8
  • WEAWEL1=8
  • WEBWEU0=8
  • WEBWEU1=8
 RAMB8BWER_RAMB8BWER
  • ADDRAWRADDR0=8
  • ADDRAWRADDR1=8
  • ADDRAWRADDR10=8
  • ADDRAWRADDR11=8
  • ADDRAWRADDR12=8
  • ADDRAWRADDR2=8
  • ADDRAWRADDR3=8
  • ADDRAWRADDR4=8
  • ADDRAWRADDR5=8
  • ADDRAWRADDR6=8
  • ADDRAWRADDR7=8
  • ADDRAWRADDR8=8
  • ADDRAWRADDR9=8
  • ADDRBRDADDR0=8
  • ADDRBRDADDR1=8
  • ADDRBRDADDR10=8
  • ADDRBRDADDR11=8
  • ADDRBRDADDR12=8
  • ADDRBRDADDR2=8
  • ADDRBRDADDR3=8
  • ADDRBRDADDR4=8
  • ADDRBRDADDR5=8
  • ADDRBRDADDR6=8
  • ADDRBRDADDR7=8
  • ADDRBRDADDR8=8
  • ADDRBRDADDR9=8
  • CLKAWRCLK=8
  • CLKBRDCLK=8
  • DIADI0=8
  • DIADI1=8
  • DIADI10=8
  • DIADI11=8
  • DIADI12=8
  • DIADI13=8
  • DIADI14=8
  • DIADI15=8
  • DIADI2=8
  • DIADI3=8
  • DIADI4=8
  • DIADI5=8
  • DIADI6=8
  • DIADI7=8
  • DIADI8=8
  • DIADI9=8
  • DIBDI0=8
  • DIBDI1=8
  • DIBDI10=8
  • DIBDI11=8
  • DIBDI12=8
  • DIBDI13=8
  • DIBDI14=8
  • DIBDI15=8
  • DIBDI2=8
  • DIBDI3=8
  • DIBDI4=8
  • DIBDI5=8
  • DIBDI6=8
  • DIBDI7=8
  • DIBDI8=8
  • DIBDI9=8
  • DIPADIP0=8
  • DIPADIP1=8
  • DIPBDIP0=8
  • DIPBDIP1=8
  • DOADO0=8
  • DOADO1=8
  • DOADO10=8
  • DOADO11=8
  • DOADO2=8
  • DOADO3=8
  • DOADO8=8
  • DOADO9=8
  • DOBDO0=8
  • DOBDO1=8
  • DOBDO10=8
  • DOBDO11=8
  • DOBDO2=8
  • DOBDO3=8
  • DOBDO8=8
  • DOBDO9=8
  • ENAWREN=8
  • ENBRDEN=8
  • REGCEA=8
  • REGCEBREGCE=8
  • RSTA=8
  • RSTBRST=8
  • WEAWEL0=8
  • WEAWEL1=8
  • WEBWEU0=8
  • WEBWEU1=8
 REG_SR
  • CE=1087
  • CK=4348
  • D=4348
  • Q=4348
  • SR=404
 SELMUX2_1
  • 0=13
  • 1=13
  • OUT=13
  • S0=13
 SLICEL
  • A=2
  • A1=44
  • A2=50
  • A3=275
  • A4=305
  • A5=327
  • A6=386
  • AMUX=11
  • AQ=339
  • AX=69
  • B=4
  • B1=52
  • B2=66
  • B3=310
  • B4=342
  • B5=363
  • B6=381
  • BMUX=17
  • BQ=377
  • BX=71
  • C1=42
  • C2=55
  • C3=283
  • C4=330
  • C5=350
  • C6=373
  • CE=21
  • CIN=314
  • CLK=388
  • CMUX=29
  • COUT=314
  • CQ=370
  • CX=84
  • D=4
  • D1=54
  • D2=71
  • D3=288
  • D4=323
  • D5=342
  • D6=353
  • DMUX=32
  • DQ=356
  • DX=85
  • SR=13
 SLICEM
  • A1=178
  • A2=178
  • A3=178
  • A4=179
  • A5=179
  • A6=179
  • AI=178
  • AMUX=176
  • AQ=179
  • AX=176
  • B=1
  • B1=176
  • B2=176
  • B3=176
  • B4=176
  • B5=176
  • B6=176
  • BI=176
  • BMUX=168
  • BQ=177
  • BX=170
  • C=1
  • C1=176
  • C2=177
  • C3=177
  • C4=177
  • C5=177
  • C6=177
  • CE=179
  • CI=176
  • CLK=179
  • CMUX=105
  • CQ=113
  • CX=169
  • D=1
  • D1=177
  • D2=178
  • D3=178
  • D4=178
  • D5=178
  • D6=178
  • DI=177
  • DMUX=105
  • DQ=113
  • DX=168
  • WE=40
 SLICEX
  • A=176
  • A1=291
  • A2=361
  • A3=470
  • A4=520
  • A5=626
  • A6=527
  • AMUX=420
  • AQ=763
  • AX=382
  • B=178
  • B1=208
  • B2=265
  • B3=335
  • B4=381
  • B5=491
  • B6=401
  • BMUX=306
  • BQ=613
  • BX=372
  • C=57
  • C1=118
  • C2=141
  • C3=170
  • C4=214
  • C5=305
  • C6=202
  • CE=306
  • CLK=802
  • CMUX=193
  • CQ=501
  • CX=324
  • D=46
  • D1=99
  • D2=129
  • D3=153
  • D4=181
  • D5=271
  • D6=181
  • DMUX=200
  • DQ=447
  • DX=300
  • SR=157
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 5 5 0 0 0 0 0
bitgen 927 927 0 0 0 0 0
map 954 940 0 0 0 0 0
netgen 184 184 0 0 0 0 0
ngc2edif 12 12 0 0 0 0 0
ngcbuild 191 191 0 0 0 0 0
ngdbuild 964 964 0 0 0 0 0
obngc 184 184 0 0 0 0 0
par 940 940 0 0 0 0 0
trce 927 927 0 0 0 0 0
xst 1312 1312 0 0 0 0 0
 
Help Statistics
Search words with results
explicit ( 1 ) explicit power ( 1 )
power ( 1 ) power up ( 1 )
reset ( 1 )
Help files
/doc/usenglish/isehelp/cgn_c_cust_gui_overview.htm ( 2 ) /doc/usenglish/isehelp/ise_c_imp_strategies_using_fpga_editor.htm ( 1 )
/doc/usenglish/isehelp/ite_c_overview.htm ( 1 ) /doc/usenglish/isehelp/pim_db_configuration_preferences.htm ( 1 )
/doc/usenglish/isehelp/pn_db_define_verilog_module.htm ( 1 ) /doc/usenglish/isehelp/pn_db_nsw_define_hdl_module.htm ( 1 )
/doc/usenglish/isehelp/pp_db_configuration_options.htm ( 1 ) /doc/usenglish/isehelp/pp_db_general_options.htm ( 1 )
/doc/usenglish/isehelp/pp_db_simulation_properties.htm ( 1 ) /doc/usenglish/isehelp/pp_db_xst_hdl_synthesis_options.htm ( 1 )
/doc/usenglish/isehelp/xpa_c_typesview.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/sisa_4c PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserBrowsedStrategyFiles=/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2019-09-27T11:41:42
PROP_intWbtProjectID=CB4CA30C6BB66831111BF97BC0465892 PROP_intWbtProjectIteration=4
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_selectedSimRootSourceNode_behav=work.sisa_4c
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_xilxBitgCfg_GenOpt_BinaryFile=true
PROP_DevDevice=xc6slx9 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=tqg144 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-2 PROP_PreferredLanguage=Verilog
FILE_COREGEN=7 FILE_UCF=1
FILE_VERILOG=3
 
Core Statistics
Core Type=cic_compiler_v3_0
C_C1=22 C_C2=21 C_C3=20 C_C4=20
C_C5=0 C_C6=0 C_CLK_FREQ=1 C_COMPONENT_NAME=cic1
C_DIFF_DELAY=1 C_FAMILY=spartan6 C_FILTER_TYPE=1 C_HAS_ACLKEN=0
C_HAS_ARESETN=0 C_HAS_DOUT_TREADY=0 C_HAS_ROUNDING=0 C_I1=36
C_I2=31 C_I3=27 C_I4=24 C_I5=0
C_I6=0 C_INPUT_WIDTH=17 C_MAX_RATE=32 C_MIN_RATE=32
C_M_AXIS_DATA_TDATA_WIDTH=24 C_M_AXIS_DATA_TUSER_WIDTH=1 C_NUM_CHANNELS=1 C_NUM_STAGES=4
C_OUTPUT_WIDTH=17 C_RATE=32 C_RATE_TYPE=0 C_SAMPLE_FREQ=1
C_S_AXIS_CONFIG_TDATA_WIDTH=1 C_S_AXIS_DATA_TDATA_WIDTH=24 C_USE_DSP=0 C_USE_STREAMING_INTERFACE=1
C_XDEVICEFAMILY=spartan6
Core Type=dds_compiler_v4_0
c_accumulator_width=24 c_amplitude=0 c_channels=1 c_has_ce=0
c_has_channel_index=0 c_has_phase_out=0 c_has_phasegen=1 c_has_rdy=0
c_has_rfd=0 c_has_sclr=0 c_has_sincos=1 c_latency=-1
c_mem_type=1 c_negative_cosine=0 c_negative_sine=0 c_noise_shaping=1
c_optimise_goal=0 c_output_width=14 c_outputs_required=2 c_phase_angle_width=12
c_phase_increment=1 c_phase_increment_value=1111000000000000000000_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 c_phase_offset=0 c_phase_offset_value=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0
c_por_mode=0 c_use_dsp48=0 c_xdevicefamily=spartan6
Core Type=fifo_generator_v9_3
c_add_ngc_constraint=0 c_application_type_axis=0 c_application_type_rach=0 c_application_type_rdch=0
c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0 c_axi_addr_width=32
c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1 c_axi_data_width=64
c_axi_id_width=4 c_axi_ruser_width=1 c_axi_type=0 c_axi_wuser_width=1
c_axis_tdata_width=64 c_axis_tdest_width=4 c_axis_tid_width=8 c_axis_tkeep_width=4
c_axis_tstrb_width=4 c_axis_tuser_width=4 c_axis_type=0 c_common_clock=0
c_count_type=0 c_data_count_width=14 c_default_value=BlankString c_din_width=16
c_din_width_axis=1 c_din_width_rach=32 c_din_width_rdch=64 c_din_width_wach=32
c_din_width_wdch=64 c_din_width_wrch=2 c_dout_rst_val=0 c_dout_width=8
c_enable_rlocs=0 c_enable_rst_sync=1 c_error_injection_type=0 c_error_injection_type_axis=0
c_error_injection_type_rach=0 c_error_injection_type_rdch=0 c_error_injection_type_wach=0 c_error_injection_type_wdch=0
c_error_injection_type_wrch=0 c_family=spartan6 c_full_flags_rst_val=1 c_has_almost_empty=0
c_has_almost_full=0 c_has_axi_aruser=0 c_has_axi_awuser=0 c_has_axi_buser=0
c_has_axi_rd_channel=0 c_has_axi_ruser=0 c_has_axi_wr_channel=0 c_has_axi_wuser=0
c_has_axis_tdata=0 c_has_axis_tdest=0 c_has_axis_tid=0 c_has_axis_tkeep=0
c_has_axis_tlast=0 c_has_axis_tready=1 c_has_axis_tstrb=0 c_has_axis_tuser=0
c_has_backup=0 c_has_data_count=0 c_has_data_counts_axis=0 c_has_data_counts_rach=0
c_has_data_counts_rdch=0 c_has_data_counts_wach=0 c_has_data_counts_wdch=0 c_has_data_counts_wrch=0
c_has_int_clk=0 c_has_master_ce=0 c_has_meminit_file=0 c_has_overflow=1
c_has_prog_flags_axis=0 c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_wach=0
c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0 c_has_rd_data_count=0 c_has_rd_rst=0
c_has_rst=1 c_has_slave_ce=0 c_has_srst=0 c_has_underflow=0
c_has_valid=0 c_has_wr_ack=0 c_has_wr_data_count=0 c_has_wr_rst=0
c_implementation_type=2 c_implementation_type_axis=1 c_implementation_type_rach=1 c_implementation_type_rdch=1
c_implementation_type_wach=1 c_implementation_type_wdch=1 c_implementation_type_wrch=1 c_init_wr_pntr_val=0
c_interface_type=0 c_memory_type=1 c_mif_file_name=BlankString c_msgon_val=1
c_optimization_mode=0 c_overflow_low=0 c_preload_latency=1 c_preload_regs=0
c_prim_fifo_type=8kx4 c_prog_empty_thresh_assert_val=2 c_prog_empty_thresh_assert_val_axis=1022 c_prog_empty_thresh_assert_val_rach=1022
c_prog_empty_thresh_assert_val_rdch=1022 c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022
c_prog_empty_thresh_negate_val=3 c_prog_empty_type=0 c_prog_empty_type_axis=0 c_prog_empty_type_rach=0
c_prog_empty_type_rdch=0 c_prog_empty_type_wach=0 c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0
c_prog_full_thresh_assert_val=16381 c_prog_full_thresh_assert_val_axis=1023 c_prog_full_thresh_assert_val_rach=1023 c_prog_full_thresh_assert_val_rdch=1023
c_prog_full_thresh_assert_val_wach=1023 c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023 c_prog_full_thresh_negate_val=16380
c_prog_full_type=0 c_prog_full_type_axis=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0
c_prog_full_type_wach=0 c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_rach_type=0
c_rd_data_count_width=15 c_rd_depth=32768 c_rd_freq=1 c_rd_pntr_width=15
c_rdch_type=0 c_reg_slice_mode_axis=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0
c_reg_slice_mode_wach=0 c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_synchronizer_stage=2
c_underflow_low=0 c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0
c_use_dout_rst=1 c_use_ecc=0 c_use_ecc_axis=0 c_use_ecc_rach=0
c_use_ecc_rdch=0 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_embedded_reg=0 c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_valid_low=0
c_wach_type=0 c_wdch_type=0 c_wr_ack_low=0 c_wr_data_count_width=14
c_wr_depth=16384 c_wr_depth_axis=1024 c_wr_depth_rach=16 c_wr_depth_rdch=1024
c_wr_depth_wach=16 c_wr_depth_wdch=1024 c_wr_depth_wrch=16 c_wr_freq=1
c_wr_pntr_width=14 c_wr_pntr_width_axis=10 c_wr_pntr_width_rach=4 c_wr_pntr_width_rdch=10
c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4 c_wr_response_latency=1
c_wrch_type=0
Core Type=fifo_generator_v9_3
c_add_ngc_constraint=0 c_application_type_axis=0 c_application_type_rach=0 c_application_type_rdch=0
c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0 c_axi_addr_width=32
c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1 c_axi_data_width=64
c_axi_id_width=4 c_axi_ruser_width=1 c_axi_type=0 c_axi_wuser_width=1
c_axis_tdata_width=64 c_axis_tdest_width=4 c_axis_tid_width=8 c_axis_tkeep_width=4
c_axis_tstrb_width=4 c_axis_tuser_width=4 c_axis_type=0 c_common_clock=1
c_count_type=0 c_data_count_width=4 c_default_value=BlankString c_din_width=16
c_din_width_axis=1 c_din_width_rach=32 c_din_width_rdch=64 c_din_width_wach=32
c_din_width_wdch=64 c_din_width_wrch=2 c_dout_rst_val=0 c_dout_width=16
c_enable_rlocs=0 c_enable_rst_sync=1 c_error_injection_type=0 c_error_injection_type_axis=0
c_error_injection_type_rach=0 c_error_injection_type_rdch=0 c_error_injection_type_wach=0 c_error_injection_type_wdch=0
c_error_injection_type_wrch=0 c_family=spartan6 c_full_flags_rst_val=1 c_has_almost_empty=0
c_has_almost_full=0 c_has_axi_aruser=0 c_has_axi_awuser=0 c_has_axi_buser=0
c_has_axi_rd_channel=0 c_has_axi_ruser=0 c_has_axi_wr_channel=0 c_has_axi_wuser=0
c_has_axis_tdata=0 c_has_axis_tdest=0 c_has_axis_tid=0 c_has_axis_tkeep=0
c_has_axis_tlast=0 c_has_axis_tready=1 c_has_axis_tstrb=0 c_has_axis_tuser=0
c_has_backup=0 c_has_data_count=0 c_has_data_counts_axis=0 c_has_data_counts_rach=0
c_has_data_counts_rdch=0 c_has_data_counts_wach=0 c_has_data_counts_wdch=0 c_has_data_counts_wrch=0
c_has_int_clk=0 c_has_master_ce=0 c_has_meminit_file=0 c_has_overflow=0
c_has_prog_flags_axis=0 c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_wach=0
c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0 c_has_rd_data_count=0 c_has_rd_rst=0
c_has_rst=1 c_has_slave_ce=0 c_has_srst=0 c_has_underflow=0
c_has_valid=0 c_has_wr_ack=0 c_has_wr_data_count=0 c_has_wr_rst=0
c_implementation_type=0 c_implementation_type_axis=1 c_implementation_type_rach=1 c_implementation_type_rdch=1
c_implementation_type_wach=1 c_implementation_type_wdch=1 c_implementation_type_wrch=1 c_init_wr_pntr_val=0
c_interface_type=0 c_memory_type=1 c_mif_file_name=BlankString c_msgon_val=1
c_optimization_mode=0 c_overflow_low=0 c_preload_latency=1 c_preload_regs=0
c_prim_fifo_type=512x36 c_prog_empty_thresh_assert_val=2 c_prog_empty_thresh_assert_val_axis=1022 c_prog_empty_thresh_assert_val_rach=1022
c_prog_empty_thresh_assert_val_rdch=1022 c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022
c_prog_empty_thresh_negate_val=3 c_prog_empty_type=0 c_prog_empty_type_axis=0 c_prog_empty_type_rach=0
c_prog_empty_type_rdch=0 c_prog_empty_type_wach=0 c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0
c_prog_full_thresh_assert_val=14 c_prog_full_thresh_assert_val_axis=1023 c_prog_full_thresh_assert_val_rach=1023 c_prog_full_thresh_assert_val_rdch=1023
c_prog_full_thresh_assert_val_wach=1023 c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023 c_prog_full_thresh_negate_val=13
c_prog_full_type=0 c_prog_full_type_axis=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0
c_prog_full_type_wach=0 c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_rach_type=0
c_rd_data_count_width=4 c_rd_depth=16 c_rd_freq=1 c_rd_pntr_width=4
c_rdch_type=0 c_reg_slice_mode_axis=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0
c_reg_slice_mode_wach=0 c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_synchronizer_stage=2
c_underflow_low=0 c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0
c_use_dout_rst=1 c_use_ecc=0 c_use_ecc_axis=0 c_use_ecc_rach=0
c_use_ecc_rdch=0 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_embedded_reg=0 c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_valid_low=0
c_wach_type=0 c_wdch_type=0 c_wr_ack_low=0 c_wr_data_count_width=4
c_wr_depth=16 c_wr_depth_axis=1024 c_wr_depth_rach=16 c_wr_depth_rdch=1024
c_wr_depth_wach=16 c_wr_depth_wdch=1024 c_wr_depth_wrch=16 c_wr_freq=1
c_wr_pntr_width=4 c_wr_pntr_width_axis=10 c_wr_pntr_width_rach=4 c_wr_pntr_width_rdch=10
c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4 c_wr_response_latency=1
c_wrch_type=0
Core Type=fir_compiler_v6_3
c_accum_op_path_widths=34 c_accum_path_widths=34 c_channel_pattern=fixed c_coef_file=fname.mif
c_coef_file_lines=15 c_coef_mem_packing=0 c_coef_memtype=2 c_coef_path_sign=0
c_coef_path_src=0 c_coef_path_widths=17 c_coef_reload=0 c_coef_width=17
c_col_config=1 c_col_mode=1 c_col_pipe_len=4 c_component_name=fir
c_config_packet_size=0 c_config_sync_mode=0 c_config_tdata_width=1 c_data_has_tlast=0
c_data_mem_packing=0 c_data_memtype=0 c_data_path_sign=0 c_data_path_src=0
c_data_path_widths=16 c_data_width=16 c_datapath_memtype=2 c_decim_rate=2
c_elaboration_dir=masked_value c_ext_mult_cnfg=none c_filter_type=7 c_filts_packed=0
c_has_aclken=0 c_has_aresetn=0 c_has_config_channel=0 c_input_rate=32
c_interp_rate=1 c_ipbuff_memtype=2 c_latency=74 c_m_data_has_tready=0
c_m_data_has_tuser=0 c_m_data_tdata_width=24 c_m_data_tuser_width=1 c_mem_arrangement=1
c_num_channels=1 c_num_filts=1 c_num_madds=1 c_num_reload_slots=1
c_num_taps=55 c_opbuff_memtype=0 c_opt_madds=none c_optimization=0
c_output_path_widths=24 c_output_rate=64 c_output_width=24 c_oversampling_rate=15
c_reload_tdata_width=1 c_round_mode=7 c_s_data_has_fifo=1 c_s_data_has_tuser=0
c_s_data_tdata_width=16 c_s_data_tuser_width=1 c_symmetry=1 c_xdevicefamily=spartan6
c_zero_packing_factor=1
Core Type=mult_gen_v11_2
c_a_type=0 c_a_width=16 c_b_type=0 c_b_value=10000001
c_b_width=14 c_ccm_imp=0 c_ce_overrides_sclr=0 c_has_ce=0
c_has_sclr=0 c_has_zero_detect=0 c_latency=4 c_model_type=0
c_mult_type=1 c_optimize_goal=1 c_out_high=28 c_out_low=12
c_round_output=0 c_round_pt=0 c_verbosity=0 c_xdevicefamily=spartan6
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_DSP48A1=16 NGDBUILD_NUM_FD=2444
NGDBUILD_NUM_FDC=124 NGDBUILD_NUM_FDCE=179 NGDBUILD_NUM_FDE=1098 NGDBUILD_NUM_FDP=110
NGDBUILD_NUM_FDPE=2 NGDBUILD_NUM_FDR=8 NGDBUILD_NUM_FDRE=2184 NGDBUILD_NUM_FDS=48
NGDBUILD_NUM_FDSE=48 NGDBUILD_NUM_GND=60 NGDBUILD_NUM_IBUF=51 NGDBUILD_NUM_INV=142
NGDBUILD_NUM_IOBUF=8 NGDBUILD_NUM_LD=24 NGDBUILD_NUM_LUT1=178 NGDBUILD_NUM_LUT2=1329
NGDBUILD_NUM_LUT3=1673 NGDBUILD_NUM_LUT4=471 NGDBUILD_NUM_LUT5=144 NGDBUILD_NUM_LUT6=526
NGDBUILD_NUM_MUXCY=354 NGDBUILD_NUM_MUXCY_L=1120 NGDBUILD_NUM_MUXF7=13 NGDBUILD_NUM_OBUF=9
NGDBUILD_NUM_RAM16X1D=128 NGDBUILD_NUM_RAM32X1D=128 NGDBUILD_NUM_RAMB16BWER=17 NGDBUILD_NUM_RAMB8BWER=8
NGDBUILD_NUM_SRLC16E=891 NGDBUILD_NUM_VCC=27 NGDBUILD_NUM_XORCY=1422
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_DSP48A1=16 NGDBUILD_NUM_FD=2444 NGDBUILD_NUM_FDC=124
NGDBUILD_NUM_FDCE=179 NGDBUILD_NUM_FDE=1098 NGDBUILD_NUM_FDP=110 NGDBUILD_NUM_FDPE=2
NGDBUILD_NUM_FDR=8 NGDBUILD_NUM_FDRE=2184 NGDBUILD_NUM_FDS=48 NGDBUILD_NUM_FDSE=48
NGDBUILD_NUM_GND=60 NGDBUILD_NUM_IBUF=59 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=142
NGDBUILD_NUM_LD=24 NGDBUILD_NUM_LUT1=178 NGDBUILD_NUM_LUT2=1329 NGDBUILD_NUM_LUT3=1673
NGDBUILD_NUM_LUT4=471 NGDBUILD_NUM_LUT5=144 NGDBUILD_NUM_LUT6=526 NGDBUILD_NUM_MUXCY=354
NGDBUILD_NUM_MUXCY_L=1120 NGDBUILD_NUM_MUXF7=13 NGDBUILD_NUM_OBUF=9 NGDBUILD_NUM_OBUFT=8
NGDBUILD_NUM_RAMB16BWER=17 NGDBUILD_NUM_RAMB8BWER=8 NGDBUILD_NUM_SRLC16E=891 NGDBUILD_NUM_TS_TIMESPEC=1
NGDBUILD_NUM_VCC=27 NGDBUILD_NUM_XORCY=1422
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx9-2-tqg144
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto
-safe_implementation=No -fsm_style=LUT -ram_extract=Yes -ram_style=Auto
-rom_extract=Yes -shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO
-resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto -iobuf=YES
-max_fanout=100000 -bufg=16 -register_duplication=YES -register_balancing=No
-optimize_primitives=NO -use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto
-iob=Auto -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5