| Device Utilization Summary | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers |
6,000 |
11,440 |
52% |
|
| Number used as Flip Flops |
5,976 |
|
|
|
| Number used as Latches |
24 |
|
|
|
| Number used as Latch-thrus |
0 |
|
|
|
| Number used as AND/OR logics |
0 |
|
|
|
| Number of Slice LUTs |
4,041 |
5,720 |
70% |
|
| Number used as logic |
2,856 |
5,720 |
49% |
|
| Number using O6 output only |
1,171 |
|
|
|
| Number using O5 output only |
172 |
|
|
|
| Number using O5 and O6 |
1,513 |
|
|
|
| Number used as ROM |
0 |
|
|
|
| Number used as Memory |
707 |
1,440 |
49% |
|
| Number used as Dual Port RAM |
256 |
|
|
|
| Number using O6 output only |
0 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
256 |
|
|
|
| Number used as Single Port RAM |
0 |
|
|
|
| Number used as Shift Register |
451 |
|
|
|
| Number using O6 output only |
27 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
424 |
|
|
|
| Number used exclusively as route-thrus |
478 |
|
|
|
| Number with same-slice register load |
466 |
|
|
|
| Number with same-slice carry load |
12 |
|
|
|
| Number with other load |
0 |
|
|
|
| Number of occupied Slices |
1,361 |
1,430 |
95% |
|
| Number of MUXCYs used |
1,528 |
2,860 |
53% |
|
| Number of LUT Flip Flop pairs used |
4,715 |
|
|
|
| Number with an unused Flip Flop |
381 |
4,715 |
8% |
|
| Number with an unused LUT |
674 |
4,715 |
14% |
|
| Number of fully used LUT-FF pairs |
3,660 |
4,715 |
77% |
|
| Number of unique control sets |
207 |
|
|
|
Number of slice register sites lost
to control set restrictions |
589 |
11,440 |
5% |
|
| Number of bonded IOBs |
69 |
102 |
67% |
|
| Number of LOCed IOBs |
69 |
69 |
100% |
|
| Number of RAMB16BWERs |
5 |
32 |
15% |
|
| Number of RAMB8BWERs |
8 |
64 |
12% |
|
| Number of BUFIO2/BUFIO2_2CLKs |
0 |
32 |
0% |
|
| Number of BUFIO2FB/BUFIO2FB_2CLKs |
0 |
32 |
0% |
|
| Number of BUFG/BUFGMUXs |
2 |
16 |
12% |
|
| Number used as BUFGs |
2 |
|
|
|
| Number used as BUFGMUX |
0 |
|
|
|
| Number of DCM/DCM_CLKGENs |
0 |
4 |
0% |
|
| Number of ILOGIC2/ISERDES2s |
0 |
200 |
0% |
|
| Number of IODELAY2/IODRP2/IODRP2_MCBs |
0 |
200 |
0% |
|
| Number of OLOGIC2/OSERDES2s |
0 |
200 |
0% |
|
| Number of BSCANs |
0 |
4 |
0% |
|
| Number of BUFHs |
0 |
128 |
0% |
|
| Number of BUFPLLs |
0 |
8 |
0% |
|
| Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
| Number of DSP48A1s |
16 |
16 |
100% |
|
| Number of ICAPs |
0 |
1 |
0% |
|
| Number of MCBs |
0 |
2 |
0% |
|
| Number of PCILOGICSEs |
0 |
2 |
0% |
|
| Number of PLL_ADVs |
0 |
2 |
0% |
|
| Number of PMVs |
0 |
1 |
0% |
|
| Number of STARTUPs |
0 |
1 |
0% |
|
| Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
| Average Fanout of Non-Clock Nets |
2.71 |
|
|
|