CHANGE LOG for Xilinx LogiCORE CIC Compiler 3.0

Release Date:  October 2, 2013 
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Table of Contents

1.   INTRODUCTION 
2.   DEVICE SUPPORT    
3.   NEW FEATURE HISTORY   
4.   RESOLVED ISSUES 
5.   KNOWN ISSUES & LIMITATIONS 
6.   TECHNICAL SUPPORT & FEEDBACK 
7.   CORE RELEASE HISTORY 
8.   LEGAL DISCLAIMER 

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1. INTRODUCTION

  This file contains the change log for all released versions of the Xilinx 
  LogiCORE IP CIC Compiler.

  For the latest core updates, see the product page at:

    http://www.xilinx.com/products/ipcenter/CIC_Compiler.htm

  For installation instructions for this release, please go to:

    http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

  For system requirements:

    http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm


2. DEVICE SUPPORT 

  2.1. ISE

    The following device families are supported by the core for this release:

    All Series 7 devices
    All Virtex-6 devices
    All Spartan-6 devices


3. NEW FEATURE HISTORY

  3.1 ISE
 
  v3.0
    - Ongoing new device support.
    - AXI4-Stream Interfaces replace old pinout
    - Maximum Input Data Width changed from 20 to 24 bits


4. RESOLVED ISSUES 

  4.1 ISE

  v3.0 
    1. CIC Compiler v3.0 may cause System Generator error during generation
      - CR 641778
    
    2. Support 24 bit input data
      - CR 542830
      - N/A


5. KNOWN ISSUES & LIMITATIONS 

  The following are known issues for this core at time of release:

  5.1 ISE
    - None

  - For a comprehensive listing of Known Issues for this core, please see the IP 
    Release Notes Guide,  
    
    www.xilinx.com/support/documentation/user_guides/xtp025.pdf


6. TECHNICAL SUPPORT & FEEDBACK

  To obtain technical support, create a WebCase at www.xilinx.com/support.
  Questions are routed to a team with expertise using this product.
  Please feel free to leave feedback on this IP under the "Leave Feedback"
  menu item in Vivado/PlanAhead.

  Xilinx provides technical support for use of this product when used
  according to the guidelines described in the core documentation, and
  cannot guarantee timing, functionality, or support of this product for
  designs that do not follow specified guidelines.


7. CORE RELEASE HISTORY

Date        By            Version      Description
================================================================================
10/02/2013  Xilinx, Inc.  3.0          ISE 14.7 support and Production support for Series 7
06/19/2012  Xilinx, Inc.  3.0          ISE 14.6 support
03/20/2012  Xilinx, Inc.  3.0          ISE 14.5 support. 
12/18/2012  Xilinx, Inc.  3.0          ISE 14.4 and Vivado 2012.4 support
10/16/2012  Xilinx, Inc.  3.0          ISE 14.3 and Vivado 2012.3 support
07/25/2012  Xilinx, Inc.  3.0          ISE 14.2 and Vivado 2012.2 support
04/24/2012  Xilinx, Inc.  3.0          ISE 14.1 and Vivado 2012.1 support
01/11/2012  Xilinx, Inc.  3.0          ISE 13.4 support
10/19/2011  Xilinx, Inc.  3.0          ISE 13.3 support
06/22/2011  Xilinx, Inc.  3.0          ISE 13.2 support, AXI4-Stream interface, 24 bit input data
10/29/2010  Xilinx, Inc.  2.0          ISE 7 Series Monthly Snapshot - (O.28)
04/19/2010  Xilinx, Inc.  2.0          12.1 support, Virtex-6Q and Spartan-6Q support
12/02/2009  Xilinx, Inc.  1.3          11.4 support, Spartan-6L support and Automotive Spartan6 support
09/16/2009  Xilinx, Inc.  1.3          11.3 support, Virtex-6/6L and Spartan-6 support
04/25/2008  Xilinx, Inc.  1.2          Patch Release
03/24/2008  Xilinx, Inc.  1.1          Patch Release
10/10/2007  Xilinx, Inc.  1.0          Initial Release
================================================================================


8. LEGAL DISCLAIMER

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