sisa_4c Project Status
Project File: | sisa_4c.xise | Parser Errors: | No Errors
Module Name: | sisa_4c | Implementation State: | Programming File Generated
Target Device: | xc6slx9-2tqg144 | Errors: | No Errors
Product Version: | ISE 14.7 | Warnings: | 257 Warnings (0 new)
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: | All Constraints Met
Environment: | System Settings | Final Timing Score: | 0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 6,027 | 11,440 | 52% |
Number used as Flip Flops | 6,003 |  |  |
Number used as Latches | 24 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 0 |  |  |
Number of Slice LUTs | 4,058 | 5,720 | 70% |
Number used as logic | 2,880 | 5,720 | 50% |
Number using O6 output only | 1,176 |  |  |
Number using O5 output only | 180 |  |  |
Number using O5 and O6 | 1,524 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 707 | 1,440 | 49% |
Number used as Dual Port RAM | 256 |  |  |
Number using O6 output only | 0 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 256 |  |  |
Number used as Single Port RAM | 0 |  |  |
Number used as Shift Register | 451 |  |  |
Number using O6 output only | 27 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 424 |  |  |
Number used exclusively as route-thrus | 471 |  |  |
Number with same-slice register load | 459 |  |  |
Number with same-slice carry load | 12 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 1,386 | 1,430 | 96% |
Number of MUXCYs used | 1,532 | 2,860 | 53% |
Number of LUT Flip Flop pairs used | 4,754 |  |  |
Number with an unused Flip Flop | 393 | 4,754 | 8% |
Number with an unused LUT | 696 | 4,754 | 14% |
Number of fully used LUT-FF pairs | 3,665 | 4,754 | 77% |
Number of unique control sets | 208 |  |  |
Number of slice register sites lost to control set restrictions | 594 | 11,440 | 5% |
Number of bonded IOBs | 69 | 102 | 67% |
Number of LOCed IOBs | 69 | 69 | 100% |
Number of RAMB16BWERs | 17 | 32 | 53% |
Number of RAMB8BWERs | 8 | 64 | 12% |
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 2 | 16 | 12% |
Number used as BUFGs | 2 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% |
Number of ILOGIC2/ISERDES2s | 0 | 200 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% |
Number of OLOGIC2/OSERDES2s | 0 | 200 | 0% |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 16 | 16 | 100% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 0 | 2 | 0% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 2.77 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Wed May 26 10:52:01 2021 | 0 | 167 Warnings (0 new) | 93 Infos (0 new)
Translation Report | Current | Wed May 26 10:52:11 2021 | 0 | 88 Warnings (0 new) | 0
Map Report | Current | Wed May 26 11:41:31 2021 | 0 | 1 Warning (0 new) | 8 Infos (0 new)
Place and Route Report | Current | Wed May 26 11:42:23 2021 | 0 | 0 | 0
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | Wed May 26 11:42:34 2021 | 0 | 0 | 3 Infos (0 new)
Bitgen Report | Current | Wed May 26 11:42:53 2021 | 0 | 1 Warning (0 new) | 1 Info (0 new)

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Current | Wed May 26 11:42:54 2021
WebTalk Log File | Current | Wed May 26 11:42:58 2021

Date Generated: 05/26/2021 - 16:24:30