s5scc/DMA: PC communications card for the fast packet ===================================================== Marko Kovacevic,S57MMK !!! preliminary !!! !!! do not copy !!! 1. Introduction Broadening of the S5 packet network to transfer rates above 1M bps has put the users of cheap PC computers in front of a problem of a lack of solution for the user's approach on that speed. Right after Matjaz's (S53MV) publication of PSK stations designs and for the additions for Supervozelj node I wanted to find out what has been done in the world so far, which could be useful in the conditions of S5 packet. I had two basic demands in my mind: first, hardware equipment must enable sufficiently fast transfer of data between the serial controller and PC memory, and second, hardware equipment must be supported by a software drivers for as wide as possible palette of programming platforms (DOS,Linux,xNos). This other demand derives from the fact that a very small number of S5 packet enthusiasts is ready to start writing a software drivers or applications for amateur packet radio. Any unique solution would mean year-long resolving of this problem and would restrict the use of Matjaz's accomplishments. Simple arithmetic show us that at transfer rates above 100K bps intervention of the central processor cannot be applied for transfers of data from or to serial controller. On some programming platforms this limit is even lower, e.g. 19K2 Bps at Linux systems, which are more and more present on amateur desks. This leaves us with only two options of implementation of PC packet communications controller: direct DMA transfer of data or transfer of data via dual port memory. The solution with DMA transfer of data is simple and cheap. PC computers are equipped with multichannel DMA controller, which is usually unoccupied (only floppy disk controllers and sound cards use it). The transfer of several million byte/sec is practically possible, however it overcomes present needs. A disadvantage of this solution is a number of interrupts still worth mentioning, which the central processor receives. The interrupts are caused by access timing to the packet network, switch RX/TX etc. The fast PSK stations enable also a quick switch RX/TX, which requires timing parameters for network access with resolution of 1 msec. Unfortunately PC computers don't have free timing devices, which we would use for this purpose. That is why a card organized in such a way must also contain timing programmable devices. The most interesting and renowned example of a card founded in such a way is a PI2 card, which has been developed by the members of Ottawa radio amateur club. The card is supported by software drivers practically for all the important programming platforms. The solution of the packet communication card with the transfer of data via memory with dual port would be useful in the long run. From the system point of view it is a much more efficient card than card with direct DMA transfer. This kind of card would support further speed ups of S5 packet network without any problems . The best example of a card organized in such a way is PC Ethernet controller, which easily reaches the speeds of 10 Mbps. Practically all the communication cards for the industrial networks, which usually work at speed of 1M5 bps, are organized in this way. Unfortunately this solution is much more technically demanding and more expensive. On this kind of card we would have a local processor, which would take care of receive or transmit of packets. It would communicate with a central processor via memory with dual port. The interrupts of the central processor are here just an exceptional thing. An example of this kind of a card is known under the name of VANESSA(HB9). Unfortunately, Z80 is used for the local processor which heavily limits the use in S5 conditions. The card is very poorly supported by software drivers. Having considered all the arguments above I have decided to make a card, which would be from the software view compatible with PI2 card. I've also decided to implement additional selectable option, which enables setting of register structure of the card with USCC(Baycom), which will enable us to use very reliable software driver TFPCX at least on the slow channel. The card should have a communications channel for the medium transfer rate (2400 - 76800 bps) and DMA communications channel for the high transfer rates (upto 2 Mbps). 2. ISA bus Before I start describing the card let's have a look at the basic features of the ISA (Industry Standard Architecture) bus, through which the central processor of PC computers communicates with peripheral devices. Regardless of the exceptionally bad critic of the experts, the ISA bus is very renowned in the world. Numerous producers, especially from the Far East, have begun to produce all kinds of cheap central and peripheral computer units compatible with ISA bus. Unfortunately, the bus was made at the end of the seventies and does not fit the modern needs of reliability, transfer rate and system functionality. That is why a few years ago there has been a demand for new, more efficient and more reliable bus, today known as PCI bus. Considering the fact that there will be old PC computers on most of amateur's desks for some more time, I have decided to make a new communications card on the old ISA bus. ISA bus enables next functions: - 8 or 16 bit transfer of data - addressing upto 16 Mbyte of memory space - addressing 768 bytes of I/0 space - 10 interrupt lines - 7 DMA channels, three of them are 8 bit - asynchronous control of the duration of memory and I/O read or write cycles - power supply of the peripheral units A special unpleasant feature of this bus is a very poor electrical and timing definition of the signals of the bus, which represents a very tough problem for the developers of central and peripheral computer units and for the system integrators. I have also met this problem when the developing card didn't work reliably on all the available PC computers. The bus is defined as 8 bit based on 62 pin edge connector with 16 bit addition based on 36 pin edge connector. The transfer of data takes place on 8 or 16 data lines SD0 - SD7 and SD8 - SD15. All 8 bit transfers take place on data lines SD0 - SD7. Addressing takes place via address lines SA0 - SA19(ISA) and LA17 - LA23 (16bit ISA). Validity of the address lines indicates the signal BALE(active 1). The address lines SA0 - SA19 latches with negative transit of the signal BALE and are valid till the end of read/write cycle. The address lines LA17 - LA23 are valid during the active level of BALE and can become invalid before the end of the current cycle. The difference between memory and I/0 read/write cycles is attained with two pairs of command signals: MEMR/MEMW and IOR/IOW (active 0). As a specialty in the world of computer buses we have here another two kinds of memory signals: MEMR/MEMW and SMEMR/SMEMW. SMEMR indicates a cycle which reaches the memory location in the first MB address space, MEMR/MEMW indicates a cycle which reaches the memory location in the overall 16 MB address space of the bus. The two special signals of the bus I/OCHRDY and 0WS regulate the duration of the read/write cycles on the bus. The bus contains also the protection against endless cycles. Every cycle ends after a certain time, also when I/OCHRDY and OWS are inactive. So, the bus doesn't hang up, eventhough we address a non-existent memory or I/0 location. Many peripheral units use this feature of the bus to close the cycles, which access memory or I/0 locations. This way they don't contain any logic for timing regulation of cycles. We use I/OCHRDY (active 0) for prolonging the duration of memory or I/O cycle. A cycle prolonged in such a way mustn't last more than 2.5 usec. The active level of the OWS (1) signal tells the central processor that it can immediately turn off the current read or write cycle. Picture 1 shows the diagram of the I/0 cycle timing control: a)using the I/OCHRDY signal b)using the OWS signal. Central unit of PC computer contains two interrupt controllers 8259 linked into the chain. The whole number of interrupt inputs is 15. There are 10 interrupt lines linked to the ISA bus. The five other interrupt inputs are used on the central processing unit. Interrupt lines are sensitive on the active level +5V(1). Activity of the individual interrupt input, priority and the priority resolving mode is set by software. Software service routine reaches the registers of interrupt controllers where it can mark the end of servicing of interrupts and starts new priority resolution cycle and enables further interrupts to take a place. ISA bus doesn't enable automatically reading of interrupt vector from peripheral device. 3. ISA bus and DMA Every IBM PC compatible central processing unit contains two four channel DMA controllers. On peripheral unit's request DMA controller takes over the control of the local memory bus of the central unit and over the ISA bus, so that it generates all the necessary signals (address and control) for write/read into memory and all the necessary signals for read/write from the peripheral unit on the ISA bus. Like this direct way for transfer of data between peripheral unit and central memory is established. During the DMA transfer of data the central processor retreats, which means it sets all the addresses, data and control signals into high impedance state. DMA controller contains several registers for setting the target address, source data address, number of Bytes(or words) for transfer and direction of transfer. So, before every DMA transfer of data block, we have to set all the registers of the controller by software. Peripheral devices, linked on the ISA bus request a DMA transfer so that they activate one of the control lines of the bus DRQ0 - DRQ7 (active level 1). When DMA controller senses active state of DRQ line, it demands the control over the bus from the central processor. Central processor grants use of local bus to DMA controller. According to the previous register settings DMA controller generates address and control lines for the central memory and confirms DMA transfer with corresponding signal DACK0 - DACK7 (active 0) and sets AEN signal to active level 1, which designates invalid address lines on ISA bus. At the same time DMA controller generates also control signals on the ISA bus (IOR/IOW). The timing of the read/write cycle on the ISA bus is from now on the same as at the normal cycle, only that peripheral unit is selected on the basis of DACK signal and not on the basis of address signal lines. PC DMA controllers know two kinds of DMA write cycles on the ISA bus (software selectable over the registers of the controller). The cycles differ from each other by the time of activating the data lines related to negative transit of write control signal IOW. When the data lines are activated before the negative transit of the IOW signal, we are talking about the prolonged write DMA cycle. In the other case, the data lines are active after the negative transit of the IOW signal. The second mode is usually in use, also because it is more convenient considering the transfer rate. A very unpredictable delay time of data signals after the negative transit of IOW signal also represents a special problem. This time can exceptionally reach even 1.5 usec. This fact had a very important impact on design of a circuit, especially on timing of DMA write cycles. Picture 2 represents timing of DMA write cycles on the ISA bus. 4. The description of the functions of s5scc/DMA card As it has already been said the card has been based on the example of Ottawa PI2 card (Ottawa Amateur Radio Club), which contains two communications channels (one circuit Z8530). The basic feature is DMA transfer of data between the processor of the central unit and channel A of the serial interface circuit Z8530 (SCC) on the card, which is necessary for the direct communication of PC computer to SV nodes at a rate of 1M2bps. The card is composed of next functional wholes: - interface for the ISA bus and DMA logic - SCC serial communications interface - timing circuits (8254) - Manchester modem (S53MV) -2400 to 76800 bps - Scrambler (S53MV) - 1M2 bps. Picture 3 shows block scheme of s s5scc/DMA card. The interface for ISA bus has the duty of decoding the card address, of generating of the select signals for circuits Z8530 (SCC) and 82C54 (PIC), of generating the control signals for write (LWR) and read (LRD) of the register Z8530 and 82C54, of controlling of data interface 74HC646 and adapting of DMA signals. The bus interface are made using 8 bit data interface circuit 74HC646 with D memory cells, comparator 74HC688 for decoding base card address and programmable circuit GAL22V10 for generating the select and control signals. The card occupies 16 bytes of the I/0 address space of the ISA bus. We choose the base card address on the six jumpers, which enables setting of any address. The card knows two ways of addressing the registers: USCC compatible and PI2 compatible. USCC compatible and PI2 compatible addressing of the card have different offset of the individual registers of circuits Z8530 and 82C54 from the base card address. We choose the mode of addressing on the special jumper. The selection of the base card address shows the next table. Only typical settings are shown. SW1-6 SW1-5 SW1-4 SW1-3 SW1-2 SW1-1 _____________________________________________________ 000H on on on on on on 230H off on on on off off 240H off on on off on on 300H off off on on on on 310H off off on on on off 320H off off on on off on 330H off off on on off off 380H off off off on on on 3F0H off off off off off off The next table shows the mode of addressing the registers. Offsets of the individual register from the base address according to the state of jumper J7 are written in the table, where we choose USCC(on) and PI2(off) compatible addressing of register. register J7 off J7 on description ___________________________________________________ A control 2 4 SCC port A control register A data 3 0 SCC port A data register B control 0 5 SCC port B control register B data 1 1 SCC port B data register C0 timer 8 Dh Timer, prescaler - runs C1 in C2 C1 timer 9 9h Timer, port A CTS C2 timer Ah Ch Timer, port B CTS CTL timer Bh 8h Timer control register INTA Eh Eh SCC Vectored mode, read irq vector DMADIS 4h Fh DMA disable register (not in function) We can connect interrupt signal of the serial controller SCC on the interrupt signals IRQ5, IRQ7, IRQ10, IRQ11, IRQ12 or IRQ15 of the ISA bus via jumper array. The card enables functioning of the serial communications controller SCC in "vectored" mode. By reading a special interrupt register of the card (INTA) we can get the vector of waiting interrupt with currently highest priority. We choose the interrupt level of the ISA bus by setting one of the following jumper arrays: IRQ5 J18 1 - 2 on IRQ7 J18 2 - 3 on IRQ10 J14 on IRQ11 J15 on IRQ12 J16 on IRQ15 J17 on The transfer of data between the processor and channel A of the serial communications interface is based on a DMA principle. We choose the DMA channel of the ISA bus via jumper array between DRQ0, DRQ1 and DRQ3 (8 byte DMA channels of the ISA bus). We choose DMA channel on the jumper arrays: DRQ0 J2, J5 on DRQ1 J3, J4 on DRQ3 J1, J6 on There is always only one DMA channel linked. The card PI2 contains a special register (DMADIS), which prevents the issuing of the requests for the DMA transfer to the central processor (DRQn). This register has at PI2 card function of prevention of the DMA transfers of data from/to SCC controller during the addressing of the SCC registers (register selection, write/read of the register). This way program waiting loop for assuring valid access recovery time during access of the registers of SCC controller become uninterruptable by DMA cycles. Unfortunately, this solution is to slow in the terms of transfer rates above cca 600 Kbps. That is why the solution of the problem of minimal time of standstill between the two accesses to the SCC registers (Valid Access Recovery Time) is assured by means of hardware. For this purpose the card contains a monostabile circuit 74HC123, of which one half marks the time with its output, when the access to SCC registers isn't allowed. While this output is active, the beginning of commands for read or write of registers of SCC controller is delayed. At higher transfer rates we need a punctual measurement of time at reaching PR network with a resolution of at least 1 msec. That is why S5 - SCC/DMA card contains a special timing circuit 8254. The circuit contains prescaler of the clock 4.9152 Mhz, which gives us a time base (eg. 0.5msec). For every communications channel we have another "time out" circuit, which enables setting of time constants in resolution of time base (eg.TxDelay). After the expiration of the appointed time, the circuit generates the interrupt, so that it activates the CTS input on the appropriate channel of the SCC circuit or in other words interrupt of central processor. Manchester and Scrambler modems (S53MV) are already described on pages of CQ ZRS, so I won't describe them again. Minimal changes are done only on DCD circuits. At Manchester modem histeresys is added to the comparator circuit (LM339) for decoding DCD active state (resistor R6 and R8). So the transfer of DCD signal from the active state to the inactive state and vice versa is more stabile. At Scrambler the RC net for establishing DCD active state is replaced by a monostable circuit with a time constant 100usec. Stable and quick activity of DCD circuits is very important for the packet network. This is how we can cut down the timing window where the collision at the transfer might occur, in the case when two stations hear each other. The data signals RXD are conditioned with the active level of the appropriate DCD signals. This way we eliminate reception of the noise and the unnecessary interrupts of the processor, when there's no active signal on the input of modem. 4. Timing sequence of read and write cycles All the work of designing a s5scc/dma card reduces to the interface between ISA bus and serial controller Z8530 (SCC) on the card. According to the already mentioned poor definition of ISA bus and important differences from different producers, the problem was seen as demanding, although logically very simple. It was made difficult additionally because of obsolete circuit Z8530(SCC), which demands a stabile state on data lines before the negative transit of write command signal. As already said, on the ISA bus the state of data lines is definitely stabile only before the transfer of write command to inactive state. Logical functions of interface between the ISA bus and Z8530 and 8254 circuits are implemented with the use of programmable logical circuit GAL22V10. Circuit has 10 combinatorial outputs and 12 logical inputs. Circuit is very adaptable to different needs. It is possible to reprogram it, which enables changes of logic or corrections. For programming of the circuit functions I've used tool Abel (like PALASAM). Next logical equations describe functions of the circuit: "Input pins WR,A0,A1,A2,A3,_SEL688,_RD,_DACK,SCC_PI pin 1, 2, 3, 4, 5, 6, 7, 8, 9 ; _DRQ,_WRDELAY,RECOVER pin 10, 11, 13; "I/O pins _SCC,_PIC,MUXD,_IRQA,LA0,LA1,_LRD,_LWR pin 14, 15, 16, 17, 18, 19, 20, 21 ; DRQB,RDORWR pin 22, 23; "invert for positive logic SEL688 = !_SEL688; RD = !_RD; DACK = !_DACK; DRQ = !_DRQ; SCC = !_SCC; PIC = !_PIC; IRQA = !_IRQA; LRD = !_LRD; LWR = !_LWR; WRDELAY = !_WRDELAY; equations SCC = DACK # SCC_PI & !A2 & !A3 & SEL688 # !SCC_PI & !A3 & SEL688 ; PIC = SCC_PI & !A2 & A3 & SEL688 # !SCC_PI & !A1 & A3 & SEL688 ; LA0 = SCC_PI & A0 # !SCC_PI & !A2 # DACK ; LA1 = SCC_PI & A1 # !SCC_PI & !A0 # DACK ; LRD = (DACK # SEL688) & RD & !RECOVER; LWR = SEL688 & WR & !RECOVER & WRDELAY # DACK & !WR & WRDELAY # LWR & WRDELAY & !SEL688; RDORWR = LRD # LWR; MUXD = DACK & LWR # MUXD & LWR; IRQA = SEL688 & !DACK & A3 & A2 & A1 & !A0; DRQB = DRQ & !(DACK & WRDELAY); The whole logic is activated with active output of address comparator circuit (SEL688) or with active signal DACK as an answer to a request of SCC circuit for DMA transfer. The select signals for Z8530(SCC) or 8254(PIC) are generated depending on the state of jumper array J7 (SCC_PI). This jumper enables an adjustment of addressing the registers compatible with PI2 or USCC card (look at the table in chapter 3). Regardless of the state SCC_PI the condition for the SCC circuit is logical level 0 of the address line A3 of the ISA bus, while for the select signal for the timing circuit 8254(PIC) the condition of level 1 of the address line A3 of the ISA bus is necessary . Address lines A2 and A1, which are present in equations of select signals SCC and PIC implement a different register structure compatible with PI2 or USCC. SCC select signal activates itself always, when the signal DACK is active, in other words when DMA transfer takes place. Signals LA0 and LA1 are select signals of registers of circuits SCC and PIC. Logic of these two also depends from the state of jumper J7 (SCC_PI). in the case of PI2 compatible register structure, LA0 is the same as A0 of ISA bus and LA1 the same as A1 of the ISA bus. In the case of USCC register structure LA0 is the same as inverted signal A2 of the ISA bus and LA1 the same as the inverted signal A0 of the ISA bus. This way we get a strange offsets of registers of USCC card. Signals LA0 and LA1 have the state 1 if the signal DACK is active, in other words in time of DMA transfer. This way a data register of A channel of SCC circuit is chosen. Signals LRD and LWR are command signals for reading and writing of registers of SCC and PIC circuits. At logical functions of both signals the signal RECOVER is present. This signal implements the time pause between the two commands LRD or LWR. Every transfer to inactive state LRD or LRW triggers a monostable circuit 74HC123 with a timing constant 900nsec (RECOVER). During the active state of the signal RECOVER it isn't possible to activate signals LRD or LWR. The condition for activating the read command signal is select signal of card SEL688 or DACK (DMA transfer) and active state IOR of the ISA bus. Logical function of the signal LWR is different in the case of DMA transfer and in the case when central processor writes into card registers. In both cases there is also a signal WRDELAY, which has different function at processor write cycles and different at DMA write cycles. This signal is ISA bus IOW signal delayed for 120 nsec. In the case when central processor writes into card registers (active SEL688) WRDELAY delays the transfer of LWR in active state (O), while the transfer in inactive state follows the IOW signal. In case of DMA write into register of SCC circuit (DACK signal is active) LWR generates after ISA IOW signal becomes inactive and follows the WRDELAY signal. This way we have activated write command of SCC circuit at the time when the data lines of the ISA bus by DMA write cycles are definitely stabile. Of course, we have to save the state of data lines in the moment of transfer of ISA IOW signal into inactive state. For this purpose we have 74HC646 circuit, which contains D memory cells. Circuit 74HC646 is 8 bit bi-directional interface for transfer of data between the on board data bus and ISA bus. The circuit contains also bi-directional D memory cells. The circuit has input control signals for the direction of transfer and for the transfer into the high impedance state. For every direction we also have a signal for the write into D cells and a select signal for placing of state of D cells or current state of data input lines. The circuit is open in the direction SCC - ISA bus only during the active state of LRD signal. The memory cells never activate in this direction. Otherwise this circuit is open in the direction ISA bus - SCC. The state of data lines of ISA bus are written into D cells at the transfer of IOW signal in an inactive state. State of D cells is placed on the local bus during the active state of signal MUXD during the DMA transfer. The request for DMA transfer of data (DRQn) is generated by logical function DRQB. In the case of DMA read IO cycle DMA request of SCC circuit (W/REQA) only inverts and places onto ISA bus. In the case of write DMA IO cycle the request for DMA transfer is placed onto ISA bus as inverted signal until the time constant WRDELAY (RC circuit WRDELAY) runs out. This way, with early removal of the request for the DMA transfer, we simulate conclusion of DMA cycle, eventhough the really data writing follows after the expiration of the whole ISA write cycle, when we write the state of D cells of circuit 74HC646 into data register of SCC circuit. SCC circuit contains the possibility of an automatic generation of interrupt vector(INTA). In the service interrupt routine we can find out with only one read command which of the waiting interrupt reasons of SCC circuit has the highest priority. That is why we have the decoding logical function INTA, which activates INTA input of the SCC circuit. When we are addressing a register INTA (look at the address table) SCC circuit places a code of the waiting interrupt with the highest priority onto data lines. Picture 4 shows a) timing of read cycle of the SCC registers, and b) timing of the write cycle of SCC registers. 5. Software drivers As already said, one of the main reasons for the decision for PI2 compatible card is a wide software support. On the basis of existing drivers from different authors for PI2 card, I came with relatively small adjustments to drivers for different programming platforms. Currently tested are the next software drivers for S5 - SCC/DMA card: Packet driver (FTP Software compliant, VE3IFB) - only channel A PI driver for JNOS (VE3IFB) PI2 driver for Linux Flexnet s5scc.exe driver (S57MMK) TFPCX - only channel B (no changes). Necessary changes of the original PI or PI2 drivers derive from the differences of coding data for channel A (NRZ at PI modems, NRZI at Scrambler modem for S5 net), different PCLK clock of SCC circuit (7.3728 or 3.6864 MHz at PI cards and 9.8304 MHz at s5scc) and different mode of ensuring the minimal access recovery time between the two consecutive access to SCC register. Flexnet driver (s5scc.exe) is my original work based on a dummy driver source and on a detailed knowledge of drivers for JNOS and Linux. All drivers are written in program language C except the Packet driver, which is written in the assembler. According to the newest accomplishments of the Flexnet(flex 95) programmers group for the support of AX25 under the programming platform Windows 95 (Microsoft) I have decided to end the drivers support for all the versions of NOS (JNOS, TNOS...). For the majority of users of Windows 95 platform with the flex 95 addition, driver s5scc.exe, different terminal programs (SP,GP...) and a complete TCP/IP support is a very useful platform for the AX25 and TCP/IP communications on packet network. According to the activity of the Flexnet group we can expect even more practical and pleasant solutions. For the startup of Flexnet we need a complete distribution of Flexnet kernel(Flexnet.exe, flex.exe, fset.exe, tfemu.exe with documentation, look at http://home.pages.de/~flexnet) and file s5scc.exe and s5scc.doc. For work in Windows 95 platform and use of tcp/ip protocol we need also flex95ip.lzh. The start up of the flexnet kernel, s5scc driver at the rate 76800bps of B channel, interrupt level 7 and DMA channel 3 and DRSI emulator does the following sequence of commands, which we can include in the startup file (autoexec.bat): echo OFF c:\flexnet\FLEXNET 50 if errorlevel 1 goto error c:\flexnet\s5scc 0x300 7 3 76800 if errorlevel 1 goto error c:\flexnet\FLEX c:\flexnet\fset txd 1 25 c:\flexnet\fset txd 0 4 c:\flexnet\tfemu goto end :error c:\flexnet\FLEX /u :end I have tested Software drivers for Linux on different versions of kernel (2.00 to 2.0.29). The driver is stable. AX25 implementation under Linux works efficiently. Disadvantage of the ax25 timing basis of 100 msec is unimportant in the conditions of quality links. The only true disadvantage concerns the AX25 parameter T2. In the conditions of transfer rate 1 Mbps we would need a possibility of set up T2 to 20 msec or less. I have changed AX25_timer.c program of Linux kernel, so that T2 is always 0. This way I generate some more QRM, but response times are very convenient. I completely agree with the authors of AX25 module of Linux kernel who are standing up to changes of ax25 timing basis to 10 msec, which would really slowdown the whole system. For the beginning the sufficient change would be the set up of AX25 parameter T2 to 0 with the use of standard AX25 utility programs. For the use of card under Linux it is necessary to compile the Linux kernel with the selected option for AX25 and P12 card after we copy adapted files pi2.c and pi2.h in the directory /usr/src/linux??/drivers/net. TFPCX works for the channel B completely the same as at USCC compatible cards. Before the start up of TFPCX driver it is necessary to initialize timing circuits of the card. For this purpose we have SCC_TIM.EXE program available. All the source programs, for all the enumerated platforms are accessible from S5 packet network or from internet via ftp protocol on server lea.hamradio.si/pub/s5scc.